1 ps8888a 04/26/07 features ? two high speed pci express lanes ? supports pci express data rates (2.5 gbps) on each lane ? adjustable receiver equalization ? input signal level detect & output squelch on all channels ? output de-emphasis = -3.5db ? 100?ohm differential cml i/o?s ? low power (100mw per channel) ? standby mode ? power down state ? v dd operating range: 1.8v +/-0.1v ? packaging (pb-free & green): 48-contact tqfn description pericom semiconductor?s PI2EQX4432D is a low power, pci express compliant signal re-driver. the device provides programmable equalization, to optimize performance by reducing inter-symbol interference (isi). PI2EQX4432D supports two 100? ohm differential cml data i/o?s between the protocol asic to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user?s platform. the integrated equalization circuitry provides exibility with signal integrity of the pci express signal before the re-driver. whereas the integrated de-emphasis circuitry provides exibility with signal integrity of the pci express signal after the re- driver. a low-level input signal detection and output squelch function is provided for all four channels. each channel operates fully independantly. when a channel is enabled (en_x=1) and operating, that channels input signal level (on xl+/-) determines whether the output is enabled. if the input level of the channel falls below the active threshold level (vth-) then the output driver switches off, and the pin is pulled to vdd via a high impedance resistor. in addition to providing serial re-conditioning, pericom's pieqx4432d also provides a power management stand-by mode operated by the enable pins. PI2EQX4432D 2.5 gbps x2 lane pci express repeater/equalizer with signal detect and flow-through pinout block diagram pin description (top view) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 4443 42 41 40 39 38 37 a i+ a i? vdd bo+ bo? vdd ci+ ci? vdd do+ do? vdd ao+ ao? vdd bi+ bi? vdd co+ co? vdd di+ di? gn d vdd sel?eq_a sel?eq_b sel?ol_a sel?ol_b sel?de_a sel?de_b en_a en_b en_c en_d vdd en_clk clk+ clk? sel?eq_c sel?eq_d sel?ol_c sel?ol_d sel?de_c sel?de_d clko+ clko? iref signal detect cml xo+ xo? xl+ xl? equalizer limiting amp sel?eq_x sel?ol_x sel?de_x ? ? repeat 4 times ?? clk+ clk? buffer iref clko+ clko? en_x power management en_clk clock 07-0106
2 ps8888a 04/26/07 PI2EQX4432D 2.5gbps x2 lane pci express repeater / equalizer with signal detect and flow-through pinout pin description pin # pin name i/o description 1 ai+ i positive cml input channel a with internal 50 ohm pull down during normal opera- tion (en_a = 1). when en_a = 0, this pin is a high-impedance. 2 ai- i negative cml input channel a with internal 50 ohm pull down during normal op- eration (en_a = 1). when en_a =0, this pin is a high-impedance. 36 ao+ o positive cml output channel a internal 50 ohm pull up during normal operation and 2k pull up otherwise. 35 ao- o negative cml output channel a with internal 50 ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. 33 bi+ posite cml input channel b with internal 50 ohm pull down during normal opera- tion (en_b = 1). when en_b = 0, this pin is a high-impedance. 32 bi- i negative cml input channel b with internal 50 ohm pull down during normal opera- tion (en_b = 1). when en_b = 0, this pin is a high-impedance. 4 bo+ o positive cml output channel b with internal 50 ohm pull up during normal opera- tion and 2k?ohm pull up otherwise. 5 bo- o negative cmloutput channel b with internal 50 ohm pull up during normal opera- tion and 2k?ohm pull up otherwise. 7 ci+ i positive cml input channel c with internal 50 ohm pull down during normal opera- tion (en_c = 1). when en_c = 0, this pin is a high-impedance. 8 ci- i negative cml input channel c with internal 50 ohm pull down during normal opera- tion (en_c = 1). when en_c = 0, this pin is a high-impedance. 30 co+ o positive cmloutput channel c with internal 50 ohm pull up during normal opera- tion and 2k-ohm pull up otherwise. 29 co- o negative cmloutput channel c with internal 50 ohm pull up during normal opera- tion and 2k?ohm pull up otherwise. 27 di+ i positive cml input channel d with internal 50 ohm pull down during normal opera- tion (en_d = 1). when en_d = 0, this pin is a high-impedance. 26 di- i negative cml input channel d with internal 50 ohm pull down during normal op- eration (en_d = 1). when en_d = 0, this pin is a high-impedance. 10 do+ o positive cml output channel d with internal 50 ohm pull up during normal opera- tion and 2k?ohm pull up otherwise. 11 do- o negative cml output channel d with internal 50 : pull up during normal operation and 2k?ohm pull up otherwise. 41, 40, 39, 38 en_[a, b, c, d] i en_[a:d] is a channel enable pin with internal 50k?ohm pull-up resistor. alvcmos high provides normal operation. alvcmos low selects a low power down mode. 43, 42, 20, 21 sel?de_ [a:d] i output de?emphasis con guration input for channels a, b, c and d, with internal 50k?ohm pull up.refer to table for modes. 47, 46, 16, 17 sel?eq_ [a:d] i equalizer con guration input for channels a, b, c and d, with internal 50k?ohm pull-up. refer to table for modes. 45, 44, 18, 19 sel?ol_ [a:d] i output level con guration input for channels a, b, c, and d, with internal 50k?ohm pull?up. refer to table for modes. 14, 15 clk+, clk? i differential input reference clock, typically 100mhz 22, 23 clko, clko? o differential reference clock output 13 en_clk i enable clock input with 50k?ohm pull-up. when en_clk is lvcmos high level, the clock output operates normally. when en_clk = low, the clock outputs are turned off for power savings. a clock is not required bt the data channels for opera- tion. 07-0106
3 ps8888a 04/26/07 PI2EQX4432D 2.5gbps x2 lane pci express repeater / equalizer with signal detect and flow-through pinout ac/dc electrical characteristics (v dd = 1.8 0.1v) symbol parameter conditions min. typ. max. units ps supply power all enables = lvcmos high 0.1 w all enables = lvcmos low 0.6 latency from input to output 2.0 ns cml receiver input rl rx return loss 50 mhz to 1.25 ghz 12 db v rx-diffp-p differential input peak-to- peak voltage 0.175 1.200 v v rx-cm-acp ac peak common mode input voltage 150 mv v th - signal detect threshold en_x = high 120 175 mv z rx-diff-dc dc differential input impedance 80 100 120 z rx-dc dc input impedance 40 50 60 equalization j rs residual jitter (1,2) total jitter 0.3 ulp-p deterministic jitter 0.2 j rm random jitter (1,2) 1.5 psrms storage temperature ........................................................ ?65c to +150c supply voltage to ground potential ................................... ?0.5v to +2.5v dc sig voltage ..........................................................?0.5v to v dd +0.5v current output ................................................................-25ma to +25ma power dissipation continous ......................................................... 800mw operating temperature .............................................................. 0 to +70c note: stresses greater than those listed under max i mum rat- ings may cause permanent damage to the de vice. this is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i ca tion is not implied. exposure to absolute max i mum rating con di tions for ex- tended periods may affect re li abil i ty. maximum ratings (above which useful life may be impaired. for user guide lines, not tested.) output swing control sel?ol_[a:d] output swing 01 x 1 1.2x equalizer selection sel? eq_[a:d] compliance channel 0 [0:2.5db] @ 1.25 ghz 1 [0:6.5db] @ 1.25 ghz output de-emphasis adjustment sel? de_[a:d] de-emphasis 0 0db 1 ?3.5db 24 iref i connect to 475-ohm resistor to ground when the reference clock is used. otherwise do not connect. 3, 6, 9, 12, 28, 31, 34, 37, 48 vdd pwr 1.8v supply voltage 25, center pad gnd pwr supply ground, center pad must be connected notes 1. k28.7 pattern is applied differentially at point a as shown in figure 1. 2. total jitter does not include the signal source jitter. total jitter (tj) = (14.1 rj + dj) where rj is random rms jitter and dj is maximum deterministic jitter. signal source is a k28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and k28.7 (00 11111000) or equivalent for random jitter test. residual jitter is that which remains after equalizing media-induced losses of the environment of figure 1 or its equivalent. the deterministic jitter at point b must be from media-induced loss, and not from clock source modulation. jitter is measured at 0v at point c of figure 1. 07-0106
4 ps8888a 04/26/07 PI2EQX4432D 2.5gbps x2 lane pci express repeater / equalizer with signal detect and flow-through pinout ac/dc electrical characteristics (ta = 0 to 70 ?c) symbol parameter conditions min. typ. max. units cml transmitter output (100 differential) v diffp output voltage swing differential swing | v tx-d+ - v tx-d- | 400 900 mvp-p v tx-c common-mode voltage | v tx-d+ + v tx-d- | / 2 v dd - 0.3 t f , t r transition time 20% to 80% (1) 150 ps z out output resistance single ended 40 50 60 z tx-diff-dc dc differential tx impedance 80 100 120 c tx ac coupling capacitor 75 200 nf v tx-diffp-p differential peak-to-peak ouput voltage v tx-diffp-p = 2 * | v tx-d+ - v tx-d- | 0.8 1.8 v lvcmos control pins v ih input high voltage 0.65 v dd v dd v v il input low voltage 0.35 v dd i ih input high current 250 a i il input low current 500 figure 1. test condition referenced in the electrical characteristic table signal source fr4 a b sma connector sma connector 30in pericom re?driver in out c 07-0106
5 ps8888a 04/26/07 PI2EQX4432D 2.5gbps x2 lane pci express repeater / equalizer with signal detect and flow-through pinout ac switching characteristics for clock buffer (v dd = 1.8 0.1v, av dd = 1.8 0.1v) (3) symbol parameters min max. units notes t rise / t fall rise and fall time (measured between 0.175v to 0.525v) (1) 125 525 ps 1 t rise / t fall rise and fall time variation 75 1 v high voltage high including overshoot 660 900 mv 1 v low voltage low including undershoot -200 1 v cross absolute crossing point voltages 200 550 1 v cross total variation of vcross over all edges 250 1 t dc duty cycle (input duty cycle = 50%) (2) 45 55 % 2 notes: 1. measurement taken from single ended waveform. 2. measurement taken from differential waveform. 3. test con guration is r s = 33.2, rp = 49.9 , and 2pf. con guration test load board termination figure 2. con guration test load board termination note: ? tla and tlb are 3? transmission lines. 07-0106
6 ps8888a 04/26/07 PI2EQX4432D 2.5gbps x2 lane pci express repeater / equalizer with signal detect and flow-through pinout ordering information ordering number package code package description PI2EQX4432Dzde zd pb-free & green 48-contact tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? e = pb-free & green ? x suf x = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com packaging mechanical: 48-contact tqfn (zd48) description: 48-contact, thin fine pitch quad flat no-lead (tqfn) package code: zd (zd48) document control #: pd-2045 revision: a . o t e s ! l l d i m e n s i o n s a r e i n m i l l i m e t e r s a n g l e s i n d e g r e e s 2 e f * % $ % # - /
6 + + $ 4 h e r m a l 6 i a $ i a m e t e r 2 e c o m m e n d e d ^ m m 4 h e r m a l 6 i a 0 i t c h 2 e c o m m e n d e d m m " i l a t e r a l c o p l a n a r i t y z o n e a p p l i e s t o t h e e x p o s e d h e a t s i n k s l u g a s w e l l a s t h e t e r m i n a l s date: 03/10/06 ( ( " $ % & $ ! &
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